ASML sets new EUV chipmaking density record, proposes Hyper-NA tools and radical EUV speed boosts

4500 Fab Jobs Could Go Unfilled in U.S. by 2030

TSMC’s debacle in the American desert

Intel Receives ASML’s First High NA EUV system

Meta seeks ASIC designers for ML accelerators and datacenter SoCs – Appears to be struggling to find them, even in India, as it's re-posted job ads

Chip Packaging Trumps EDA: Why Synopsys Is Paying $35 Billion For Ansys

Synopsys to acquire graphics software maker Ansys in $35 billion tech deal

Polynomial Formal Verification: Verification-Centric Strategy

5 Steps to Confront the Talent Shortage With IP-Centric Design

It’s the manufacturing, stupid!

Chip Industry Talent Shortage Drives Academic Partnerships

Google's Controversial AI Chip Paper Under Scrutiny Again

Using LLMs to Facilitate Formal Verification of RTL

Growing full wafers of high-performing 2D semiconductor that integrates with state-of-the-art chips

Test Strategies In The Era Of Heterogeneous Integration

Use Cases And Value Proposition Of eFPGA (Embedded FPGA)

Challenges In Ramping New Manufacturing Processes

Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows

The dream of a chiplet marketplace is still a long way off

Great Introduction to Formal Verification : "Formal Verification An Essential Toolkit For Modern VLSI Design"